Recently, a first-in-first-out buffer memory (FIFO) which temporarily stores communication data in sequence of receipt thereof has become indispensable and is widely used.
As is well known, FIFO is a buffer memory which stores data and from which reads the data in the order in which the data has been stored. Storing (write) and reading of data may be asynchronously performed.
An example of the above-mentioned communications network control is the Integrated Service Digital Network (ISDN) of a digital communications network which integrally handles various types of services such as telephone, telegraph, telex, data facsimile and the like. These services have recently become commercial in many countries. The communications network control involves a data link control procedure on the D channel (LAPD) in accordance with the layer 2 of ISDN or a high level data link control (HDLC) used in a link access procedure on B channel (LAPB).
The HDLC functions include, as is well known, an automatic zeroing, insertion or deletion of serial data received, inspection of the frame check sequence (FCS) and detecting of a flag abort ineffective frame.
The functions, which are required, are automatic zeroing, deletion of serial data, inspection of the frame check sequence and detection of the flag abort ineffective frame.
For displaying of the result of such inspection and detection at the receiving side, an error display system shown in FIG. 3 is widely known.
Referring to FIG. 3, the conventional error display system is composed of FIFO1 and FIFO3.
FIFO1 is a memory for accumulation of data resulting from the inspection and detection of the HDLC frame. FIFO1 is formed of 16 words with a word length of 1 byte.
FIFO3 is a memory which includes a last byte of the frame and is formed of 16 words with a word length of 1 bit.
The operation of the conventional error display system is as follows:
FIFO1 is inputted with data D1 of the HDLC frame sequentially on a one bit basis at a data input terminal TDI.
Concurrently, FIFO3 is inputted with last byte display data DE of the HDLC frame having a length of one bit at a last byte display input terminal TFI.
The input data DI and DE are written into FIFO1 and FIFO3, respectively, by FIFO write signal WR.
The data accumulated in FIFO1 are outputted from a data output terminal TDO as a data output DO.
Further, a last byte display data DE is outputted from a last byte display output terminal TFO.
The output data DO, DE of FIFO1, and FIFO3, respectively, are renewed by a FIFO data renewal signal input RN.
If the last byte display data DE inputted at the last byte display input terminal TF1 is `0`, the input data D1 fed from and in the same timing, at the data input terminal TD1, represents receiving data of the HDLC frame. If the last byte display data DE is `1`, the input data D1 is the last data of its frame.
A resultant data of the detection is accumulated in one byte next to the last data of the frame.
When no resultant is found in this error data, such fact is written in the memory.
FIG. 4 is a time chart of the system shown in FIG. 3.
Contents of the data output DO and contents of the last byte display data DE are respectively renewed at a rising edge of the FIFO data renewal signal input RN.
When the contents of the data output DO is shown by data (5) and the last byte display data DE is `1`, then error data (2) is outputted at the next rising edge.
In the conventional display system described above, with shorter frame length, in order into insert error data to one byte next to the last data, irrespective of the presence of an error in the HDLC frame, the amount of intrinsic receiving data that is stored in FIFO is decreased, therefore a drawback arises because a time interval for reading out data from the FIFO is increased.
An over-run error may occur, which would result in an inability to write received data, which is a disadvantage of the conventional display system.